> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption, However, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25 to 30 percent at the same speed, increase speed by 10 to 15 percent at the same amount of power and increase transistor density by about 33 percent compared to its previous 5 nm FinFET chips.
The same article states that transistor densities for Samsung 3nm will be 202.85 Million transistors per mm2 and for TSMC 314.73 Million transistors per mm2 so quite a big difference.
If the transistors were 2D and square then that makes Samsung's 3nm transistors actually 70nm, and TSMC's 56nm according to my maths!
Note that Samsung has abandoned FinFET for this process, and has moved to Gate-All-Around (GAA). TSMC is not yet ready to move to GAA, but will at 2nm.
I'm not sure how this changes the geometry, or the relevance of "3nm."
"The next-generation 3nm chips will be built on the Gate-All-Around (GAA) technology, which Samsung said will allow up to 45 percent area reduction while providing 30 percent higher performance and 50 percent lower power consumption, compared with the existing FinFET process."
"N2 will see TSMC switch to a nanosheet transistor architecture rather than the fin field-effect transistor (FinFET) design that has been standard in the industry for some time in order to deliver improvements in performance and power efficiency.
"The nanosheet architecture involves the electrical current flowing through several stacked layers of silicon that are completely surrounded by the transistor gate material. IBM claimed to have made the first 2nm chips using nanosheet technology last year."
"Big Blue today claimed this is “a breakthrough in semiconductor design” using nanosheet technology. That involves layering three sheets of material to form a stack containing an NMOS transistor on top of a PMOS transistor, rather than placing them side by side, commonly called a gate-all-around design. It's a step on from today's 3D FinFETs...
"It should be noted that although it’s described as being 2nm, the size of the process node is more of a naming convention to show it's smaller and more advanced than its previous 5nm design. No part of it is 2nm in size. The actual transistor gate length is 12nm."
I wonder why IBM is putting so much money into GAA when they don't even own a foundry, and their previous foundry partner has little interest in making anything smaller than 14nm.
Patents/IP. They help other companies develop their manufacturing processes. I'm sure it's a profitable enough business for it to be worth the effort, or IBM wouldn't be wasting their time with it.
My simplified layman's mental model is pixel resolution in cameras: back when we were limited only by the sensor, quadrupling megapixels would have allowed us to e.g. read a sign twice far away (ignoring noise/shake issues). Now that the resolution of the sensors usually exceeds that of the lense, more megapixels will still help us tease a little more information from the same optical projection (again, ignoring noise/shake), but those benefits are much smaller than they used to be.
With chip process node "nanometers", I assume that "the other limit" (the role taken by the lens in the camera analogy) is the size required by transistors if we had infinite resolution. Lower "nanometers" will allow us to get closer to that hypothetical best, but the benefit will be smaller and smaller.
I wonder how this naming scheme continues and why are they skipping over half the numbers given that this set will soon run to 0. 7nm - 5nm - 3nm - 1nm. What’s next?
> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption, However, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25 to 30 percent at the same speed, increase speed by 10 to 15 percent at the same amount of power and increase transistor density by about 33 percent compared to its previous 5 nm FinFET chips.
The same article states that transistor densities for Samsung 3nm will be 202.85 Million transistors per mm2 and for TSMC 314.73 Million transistors per mm2 so quite a big difference.
If the transistors were 2D and square then that makes Samsung's 3nm transistors actually 70nm, and TSMC's 56nm according to my maths!