There is a successor project as well: https://github.com/SpinalHDL/VexiiRiscv | Hacker News

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davidjade on Jan 25, 2025 | parent | context | favorite | on: A FPGA friendly 32 bit RISC-V CPU implementation

There is a successor project as well: https://github.com/SpinalHDL/VexiiRiscv

15155 on Jan 25, 2025 [–]

And a spiritual sibling: https://github.com/SpinalHDL/NaxRiscv

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